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  preliminary data sheet ac104x ac104x-ds00-405-r 16215 alton parkway ? p.o. box 57013  irvine, ca 92619-7013  phone: 949-450-8700 fax: 949-450-8710 12/11/01 2.5v 4-port 10/100-tx et hernet transceiver figure 1: functional block diagram the ac104x is a highly integrated, 2.5v, low power, four port, 10base-t/100base-tx, ethernet transceiver implemented in 0.25mm cmos technology. multiple modes of operation, including normal operation, test mode and power saving mode, are available through either hardware or software control. features include endecs, scrambler/descrambler, and auto-negotiation (aneg) with support for parallel detection. the transmitter includes a dual-speed clock synthesizer that only needs one external clock source. the chip has built-in wave shaping driver circuit for both 10mbps and 100mbps, eliminating the need for an external hybrid filter. the receiver has an adaptive equalizer / dc restoration circuit for accurate clock / data recovery for the 100base-tx signal. it also provides an on-chip low pass filer / squelch circuit for the 10base-t signal. ? 4 ports with rmii mac interface  4 ports with 10/100 tx media interface  full-duplex or half-duplex  very small package  100pqfp  very low power - typ < 280mw / port  cable detect mode - typ < 40 mw / port  power down mode - typ < 3.3 mw / port  2.5v .25 micron cmos  rmii 3.3v tolerant i/o  fully compliant with  ieee 802.3 / 802.3u rmii  baseline wander compensation  multi-function led outputs  cable length indicator  reverse polarity detection and correction with regis- ter bit indication - automatic or forced  hp auto-mdix  8 programmable interrupts port a port b port c mux mii serial management interface and registers pll clk gen. test/led control 100tx 100rx 10tx 10rx auto- negotiation rx flp 25 mhz 20 mhz control/status phyad[4:0] ckin test[3:0] led drivers 25 mhz port d rmii mdio/mdc txop/n(a) rxip/n(a) txop/n(b) rxip/n(b) txop/n(c) rxip/n(c) pcs .framer .carrier detect .4b/5b pma .clock recov. .link monitor .signal detect interface 10base-t tp_pmd .mlt-3 .blw .stream cipher txop/n(d) rxip/n(d) general description features
r evision h istory revision date change description AC104X-DS00-R 12/11/01 initial release. altima communications, inc. a wholly owned subsidiary of broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2001 altima communications, inc. all rights reserved printed in the u.s.a. b roadcom ? , the pulse logo ? , and qamlink ? are registered trademarks of broadcom corporation and/or its subsidiaries in t he united states and certain other countries. all other trademarks are the property of their respective owners. t his data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or c ertified for use in any military, nuclear, medical, mass tr ansportation, aviation, navigations, pollution control, hazardou s s ubstances management, or other high risk application. broadcom provides this data sheet "as-is", withou t w arranty of any kind. broadcom disclaims al l warranties, expressed and implied, including , w ithout limitation, the implied warranties of merchantability, fitness for a particular pur - p ose, and non-infringement.
broadcom corporation document ac104x-ds00-405-r page iii preliminary data sheet ac104x 12/11/01 t able of c ontents revision history ............................................................................................................... ........................ii section 1: functional description ...................................................................................... 1 mac interface ............................................................................................................................... ................ 1 rmii ........................................................................................................................... ............................. 1 smi............................................................................................................................ .............................. 1 interrupt...................................................................................................................... ............................. 2 media interface ............................................................................................................................... .............. 2 10base-t ....................................................................................................................... ........................ 2 transmit function .............................................................................................................. ..................... 2 receive function ............................................................................................................... ..................... 2 link monitor ................................................................................................................... ......................... 2 100base-tx..................................................................................................................... ...................... 2 transmit function .............................................................................................................. ..................... 3 parallel to serial, nrz to nrzi, and mlt3 conversion.......................................................................... 3 receive function ............................................................................................................... ..................... 3 baseline wander compensation ................................................................................................... ......... 4 clock/data recovery ............................................................................................................ .................. 4 decoder/de-scrambler ........................................................................................................... ................ 4 link monitor ................................................................................................................... ......................... 4 10base-t/100base-tx ............................................................................................................................... 5 multi-mode transmit driver..................................................................................................... ................ 5 adaptive equalizer ............................................................................................................. ..................... 5 pll clock synthesizer.......................................................................................................... .................. 5 jabber and sqe (heartbeat) ..................................................................................................... ............. 5 reverse polarity detection and correction ...................................................................................... ....... 6 initialization and setup ............................................................................................................................... .6 hardware configuration ......................................................................................................... ................. 6 software configuration ......................................................................................................... .................. 6 leds ........................................................................................................................... ............................ 6 auto-negotiation ............................................................................................................... ...................... 6 parallel detection............................................................................................................. ....................... 7 automatic mdi/mdix configuration ............................................................................................... ......... 8
broadcom corporation page iv document ac104x-ds00-405-r ac104x preliminary data sheet 12/11/01 diagnostics .................................................................................................................... .......................... 8 loopback operation ............................................................................................................. ................... 8 cable length indicator ......................................................................................................... ................... 8 reset and power ............................................................................................................................... ............ 8 clock ............................................................................................................................... ............................... 9 section 2: pin description ................................................................................................ 10 pin diagram ............................................................................................................................... ..................10 pin descriptions ............................................................................................................................... ..........11 section 3: register descriptions ..................................................................................... 16 legend......................................................................................................................... ..........................16 section 4: electrical characteristics ............................................................................... 31 absolute maximum ratings .......................................................................................................................31 operating range ............................................................................................................................... ..........31 recommended termination ......................................................................................................................37 power and ground filtering ......................................................................................................................38 section 5: package drawing ............................................................................................ 39 section 6: packaging the rmal characteristics .............................................................. 40 100pqfp package ............................................................................................................................... .......40 section 7: ordering information ..................................................................................... 41
broadcom corporation document ac104x-ds00-405-r page v preliminary data sheet ac104x 12/11/01 l ist of f igures figure 1: functional block diagram.............................................................................................. ...................i figure 2: ac104x 100-pin ........................................................................................................ ................... 10 figure 3: led configurations .................................................................................................... .................. 30 figure 4: mdc/mdio timing diagram 1............................................................................................. ......... 35 figure 5: mdc/mdio timing diagram 2............................................................................................. ......... 36 figure 6: termination figure .................................................................................................... ................... 37 figure 7: power and ground ...................................................................................................... ................. 38 figure 8: package drawing ....................................................................................................... .................. 39
broadcom corporation page vi document ac104x-ds00-405-r ac104x preliminary data sheet 12/11/01
broadcom corporation document ac104x-ds00-405-r page vii preliminary data sheet ac104x 12/11/01 l ist of t ables table 1: auto-mdi/mdix pinout assignments....................................................................................... ....... 8 table 2: mdi (media dependent interface) pins ................................................................................... ..... 11 table 3: rmii (reduced media independent interface) pins ..................................................................... 12 table 4: smi ( serial management interface) pins................................................................................ ..... 12 table 5: phy address pins ....................................................................................................... ................. 13 table 6: mode pins.............................................................................................................. ....................... 13 table 7: led pins............................................................................................................... ........................ 14 table 8: miscellaneous pins ..................................................................................................... .................. 14 table 9: power and ground pins .................................................................................................. ............. 15 table 10: registers 0-7 ......................................................................................................... ....................... 16 table 11: registers 8-31 ........................................................................................................ ...................... 17 table 12: register 0: control................................................................................................... ..................... 17 table 13: register 1: status .................................................................................................... ..................... 18 table 14: register 2: phy identifier 1 .......................................................................................... ................ 18 table 15: register 3: phy identifier 2 .......................................................................................... ................ 19 table 16: register 4: auto-negotiation advertisement ............................................................................ .... 19 table 17: register 5: auto-negotiation link partner ability register/link partner next page message ..... 20 table 18: register 6: auto-negotiation expansion................................................................................ ....... 20 table 19: register 7: auto-negotiation next page transmit....................................................................... .21 table 20: register 16: bt and interrupt level control ........................................................................... ...... 21 table 21: register 17: interrupt control/status ................................................................................. ........... 22 table 22: register 18: diagnostic ............................................................................................... ................. 23 table 23: register 19: test register ............................................................................................ ................ 24 table 24: register 20: cable measurement capability ............................................................................. ... 24 table 25: register 21: receive error counter .................................................................................... ......... 25 table 26: register 22: power management ......................................................................................... ........ 25 table 27: register 23: operation mode ........................................................................................... ............ 26 table 28: register 24: crc for recent received packet........................................................................... .26 table 29: common register 0: common operation mode (map to phy channel a, reg 28) ..................... 27 table 30: common register 1: test mode (map to phy channel a, reg 29).............................................. 27 table 31: common register 2: analog settings (map to phy channel a, reg 30) ..................................... 28 table 32: 4b/5b code-group table ................................................................................................ ............. 28
broadcom corporation page viii document ac104x-ds00-405-r ac104x preliminary data sheet 12/11/01 table 33: smi read/write sequence............................................................................................... .............29 table 34: led configurations .................................................................................................... ...................30 table 35: dc characteristics (0oc < ta < 70oc, 2.375v < vcc < 2.625v, unless otherwise noted)..........31 table 36: ac characteristics (0oc < ta < 70oc, 2.375v < vcc < 2.625v, unless otherwise noted) ..........33 table 37: digital timing characteristics (0oc preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 1: functional description page 1 section 1: functional description the ac104x physical layer device (phy) integrates the 100base- tx and 10base-t functions in a single four port chip that is used in fast ethernet 10/100 mbps applications. the 100base-tx section consists of pcs, pma, and pmd functions and the 10base-t section is consisted of manchester endec and transceiver functions. the device performs the following functions:  4b/5b  mlt3  nrzi  manchester encoding and decoding  clock and data recovery  stream cipher scrambling / de-scrambling  adaptive equalization  line transmission  carrier sense  link integrity monitor  auto-negotiation (aneg)  auto-mdi/mdix  rmii mac connectivity  mii management function it also provides an rmii consortium compatible reduced media independent interface (rmii) to communicate with an ethernet media access controller (mac). selection of 10 or 100 mbps operation is based on the settings of internal serial management interface registers or determined by the on-chip aneg logic. the device can operate in 10 or 100 mbps with full-duplex or half-duplex mode on a per-port basis. mac i nterface rmii the reduced media independent interface (rmii) is used to connect the phy with the mac. the phy and mac obtain their clock from a common 50 mhz source, such as a clock oscillator. this clock is shared by all ports within the phy for transmitting and receiving data on 2 individual 2-bit data buses. in 100m mode, rxd[1:0] is sampled on every cycle of refclk. in 10m mode, rxd[1:0] is sampled on every 10th cycle of refclk. rxer is generated by the phy to indicate a receive error to the mac. tx_en is generated by the mac to indicate to the phy when there is valid data on the transmit bus. in 100m mode, the phy will read 2 bits from txd[1:0] for each cycle of refclk. in 10m mode, the phy will read 2 bits of data from txd[1:0] every 10th cycle of refclk. the serial management interface (smi) is shared between all ports in the phy. this totals 7 pins per port plus 3 per phy. smi the phy's internal registers are accessible only through the m ii 2-wire serial management interface (smi). mdc is a clock input to the phy, which is used to latch in or out data and instructions for the phy. the clock can run from 2.5mhz to 25 mhz. mdio is a bi-directional connection used to write instructions to, write data to, or read data from the phy. each data bit is latched either in or out on the rising edge of mdc. mdc is not required to maintain any speed or duty cycle, provided no half cycle is less than 20ns and that data is presented synchronous to mdc.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 2 section 1: functional description document ac104x-ds00-405-r mdc/mdio are a common signal pair to all ports on a design. therefore, each port needs to have its own unique physical address. the physical address of the phy is set using the pins defined as phyad[4:2]. these input signals are strapped externally and sampled as reset is negated. phyad[1:0] are addressed for each port internal to the phy. internal addresses are either 00, 01, 10, 11 or 01, 10, 11, 00 depending on the polarity of phyad_st during reset. at idle, the phy is responsible to pull mdio line to a high state. therefore, a 1.5k ohm resistor is used to pull the mdio signal high. the phyad can be reprogrammed via software. a detailed definition of the serial management registers can be found in the next section. at the beginning of a read or write cycle, the mac will send a continuous 32 bits of one at the mdc clock rate to indicate preamble. a zero and a one will follow to indicate start of frame. a read op code is a one and a zero, while a write op code is a zero and a one. these will be followed by 5 bits to indicate phy address and 5 bits to indicate register address. then 2 bits follow to allow for turn around time. for read operation, the first bit will be high impedance. neither the phy nor the station will assert this bit. during the second bit time, the phy will assert this bit to a zero. for write operation, the stat ion will drive a one for the first bit time, and a zero for the second bit time. the 16 bits data field is then presented. the firs t bit that is transmitted is bit 15 of the register content. i nterrupt the intr pin on the phy will be asserted whenever one of 8 selectable interrupt events occur. selection is made by setting the appropriate bit in the upper half of the interrupt control / status register. when the intr bit goes active, the mac interface is required to read the interrupt control / status register to determine which event caused the interrupt. the status bits are read only and clear on read. when intr is not asserted, the pin is held in a high impedance state. m edia i nterface 10base-t when configured to run in 10base-t mode, either through hardwa re configuration, software c onfiguration or aneg, the phy will support all the features and parameters of the industry standards. t ransmit f unction parallel to serial logic is used to convert the 2-bit data into the serial stream. the serialized data goes directly to the manchester encoder where it is synthesized through the out put waveshaping driver. the waveshaper reduces any emi emission by filtering out the harmonics, therefore eliminating the need for an external filter. r eceive f unction the received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. this eliminates the need for a 10base-t external filter. a manchester decoder converts the incoming serial stream. serial to parallel logic is used to generate the 2-bit data. l ink m onitor the received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. this eliminates the need for a 10base-t external filter. a manchester decoder converts the incoming serial stream. serial to parallel logic is used to generate the 2-bit data. 100base-tx when configured to run in 100base-tx mode, either throu gh hardware configuration, softw are configuration or aneg.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 1: functional description page 3 t ransmit f unction in 100base-tx mode, the phy transmit function converts synchronous 2-bit data to a pair of 125 mbps differential serial data streams. the serial data is transmitted over network twis ted pair cables via an isolation transformer. data conversion includes 4b/5b encoding, scrambling, parallel to serial, nrz to nrzi, and mlt-3 encoding. the entire operation is synchronous to 25 mhz and 125 mhz clock. both clocks are generated by an on-chip pll clock synthesizer that is locked on to an external 25 mhz clock source. the transmit data is transmitted from the mac to the phy via the txd[1:0] signals. the 4b/5b encoder replaces the first two nibbles of the preamble from the mac frame with a /j/k/ code-group pair start-of-stream delimiter (ssd), following the onset of tx_en signal. the 4b/5b encoder appends a /t/r/ code-group pair end-of-stream delimiter (esd) to the end of transmission in place of the first two idle code-groups that follow the negation of the tx_en signal. the encapsulated data stream is converted from 4-bit nibbles to 5-bit code-groups. during the inter-packet gap, when there is no data present, a continuous stream of idle code-groups are transmitted. when tx_er is asserted while tx_en is active, the transmit error code-group /h/ is substituted for the translated 5b code word. the 4b/5b encoding is bypassed when reg. 21.1 is set to ?1?, or the pcsbp pin is strapped high. in 100base-tx mode, the 5-bit transmit data stream is scrambled as defined by the tp-pmd stream cipher function in order to reduce radiated emissions on the twisted pair cable. the scrambler encodes a plain text nrz bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: x[n] = x[n-11] + x[n-9] (modulo 2) the scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted frequency range, thus eliminating peaks at any single frequency. for repeater applications, where all ports transmit the same data simultaneously, signal energy is spread further by using a non-repeating sequence for each phy, i.e., the scrambled seed is unique for each different phy based on the phy address. p arallel to s erial , nrz to nrzi, and mlt3 c onversion the 5-bit nrz data is clocked into phy's shift register with a 25 mhz clock, and clocked out with a 125 mhz clock to convert it into a serial bit stream. the serial data is converted from nrz to nrzi format, which produces a transition on logic 1 and no transition on logic 0. to further reduce emi emissions, the nrzi data is converted to an mlt-3 signal. the conversion offers a 3db to 6db reduction in emi emissions. this allows system designers to meet the fcc class b limit. whenever there is a transition occurring in nrzi data, there is a corresponding transition occurring in the mlt-3 data. for nrzi data, it changes the count up/down direction after every single transition. for mlt-3 data, it changes the count up/down direction after every two transitions. the nrzi to mlt-3 data conversion is implemented without reference to the bit timing or clock information. the conversion requires detecting the transiti ons of the incoming nrzi data and setting the count up/down direction for the mlt-3 data. the slew rate of the transmitted mlt-3 signal can be controlled to reduce emi emissions. the mlt-3 signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ansi tp- pmd standard. this is guaranteed with either 1:1 or 1.25:1 transformer. r eceive f unction the 100base-tx receive path functions as the inverse of the transmit path. the receive path includes a receiver with adaptive equalization and dc restoration in the front end. it also includes a mlt-3 to nrzi converter, 125 mhz data and clock recovery, nrzi/nrz conversion, serial-to-parallel conversion, de-scrambler, and 5b/4b decoder. the receiver circuit starts with a dc bias for the differential rx+/- inputs, followed with a low-pass filter to filter out high frequency noise fro m the transmission channel media. an energy detect circuit is also added to determine whether there is any signal energy on the media. this is useful in the power-saving mode. the amplification ratio and slicer's threshold is set by the on-chip bandgap reference.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 4 section 1: functional description document ac104x-ds00-405-r b aseline w ander c ompensation the 100base-tx data stream is not always dc balanced. t he transformer blocks the dc components of the incoming signal, thus the dc offset of the differential receive inputs can drift. the shifting of the signal level, coupled with non-zer o rise and fall times of the serial stream can cause pulse-width distortion. this creates jitter and possible increase in the bit error rates. therefore, a dc restoration circuit is needed to compensate for the attenuation of the dc component. this phy implements a patent-pending dc restoration circuit. unlike t he traditional implementation, the circuit does not need the feedback information from the slicer or the clock recovery circuit. this design simplifies the circuit design and eliminates an y random/systematic offset on the receive path. in the 10baset, the baseline wander correction circuit is not required, and therefore is disabled. c lock /d ata r ecovery the equalized mlt-3 signal passes through the slicer circuit, and gets converted to nrzi format. the phy uses a proprietary mixed-signal phase locked loop (pll) to extract clock information from the incoming nrzi data. the extracted clock is used to re-time the data stream and set the data boundaries. the transmit clock is locked to the 50 mhz clock input while the receive clock is locked to the incoming data streams. when initial lock is achieved, the pll switches to the data stream, extracts the 125 mhz clock, and uses it for the bit framing for the recovered data. the pll requires no external components for its operation and has high noise immunity and low jitter. it provides fast phase alignment and locks to data in one transition. its data/clock acquisition time after power-on is less than 60 transitions. the pll can maintain lock on run - lengths of up to 60 data bits in the absence of signal transitions. when no valid data is present, i.e. when the sd is de- asserted, the pll will switch and lock on to refclk. at the pcs interface, the 5 bit data rxd[4:0] is synchronized to the 25 mhz rx_clk. d ecoder /d e -s crambler the de-scrambler detects the state of the transmit linear feedback shift register (lfsr) by looking for a sequence representing consecutive idle codes. the de-scrambler acquires lock on the data stream by recognizing idle bursts of 30 or more bits and locks its frequency to its de-ciphering lfsr. once lock is acquired, the device can operate with an inte r-packet-gap (ipg) as low as 40 ns. however, before lock is acquired, the de-scrambler needs a minimum of 270 ns of cons ecutive idles in between packets in order to acquire lock. the de-ciphering logic also tracks the number of consecutive errors received while the crs_dv is asserted. once the error counter exceeds its limit currently set to 64 consecutive errors, the logic assumes that the lock has been lost, and the de- cipher circuit resets itself. the process of regaining lock will start again. stream cipher de-scrambler is not used in the 10base-t modes. l ink m onitor signal level is detected through a squelch detection circuitry. a signal detect (sd) circuit allows the equalizer to assert hig h whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mv. this is approximately 40% of a normal signal voltage level. in addition, the energy level must be sustained for longer than 2~3 ms in order for the signal detect signal to stay on. the sd gets de-asserted approximately 1~2 ms after the energy level drops consistently below 300 mv from peak to ground. the link signal is forced low during a local loopback operation (loopback register bit is set) and forced to high when a remote loopback is taking place (en_rpbk is set). in forced 100base-tx mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor enters in the "link fail" state and nlp's are transmitted. when a valid signal is detected for a minimum period of time, the li nk monitor enters link pass state and transmits mlt-3 signal.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 1: functional description page 5 10base-t/100base-tx m ulti -m ode t ransmit d river the multi-mode driver transmits the mlt-3 coded signal in 100base-tx mode and manchester coded signal in 10base-t mode. in 10base-t mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external filter. the flp and nlp pulses are also drive out through the 10base-t driver. the 10base-t and 100base-tx transmit signals are multiplexed to the transmit output driver. this arrangement results in using the same external transformer for both the 10base-t and the 100base-tx. the driver output level is set by a built- in bandgap reference and an external resistor connected to the ibref pin. the resistor sets the output current for all modes of operation. the txop/n outputs are open drain devices with a serial source to i/o pad resistance of 10 w max. when the 1:1 transformer is used, the current rating is 40 ma for the 2vp-p mlt-3 signal, and 100 ma for the 5vp-p manchester signal. one can use a 1.25:1 transmit transformer for a 20% output driver power reduction. this will decrease the drive current to 32 ma for 100base-tx operation, and 80 ma for 10base-t operation. a daptive e qualizer the phy is designed to accommodate a maximum of 150 meters utp cat-5 cable. an at&t 1061 cat-5 cable of this length typically has an attenuation of 31 db at 100 mhz. a typical attenuation of 100-meter cable is 21 db. the worst case cable attenuation is around 24-26 db as defined by tp-pmd specification. the amplitude and phase distortion from the cable cause inter-symbol interference (isi) which makes clock and data recovery difficult. the adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable . the equalizer has the ability to changes its equalizer frequency response according to the cable length. the equalizer will tune itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. pll c lock s ynthesizer the phy includes an on-chip pll clock synthesizer that generates a 125 mhz clocks for the 100base-tx circuitry. it also generates 20 mhz and 100 mhz clocks for the 10base-t and aneg circuitry. the pll clock generator uses a fully differential vco cell that introduces very low jitter. the zero dead zone phase detection method implemented in the phy design provides excellent phase tracking. a charge pump with charge sharing compensation is also included to further reduce jitter at different loop filter vo ltages. the on-chip loop filter eliminat es the need for external components and minimizes the external noise sensitivity. only one external 50 mhz crystal or clock source is required as a reference clock. after power-on or reset, the pll clock synthesizer generates the 20 mhz clock output until the 100base-x operation mode is selected. j abber and sqe (h eartbeat ) after the mac transmitter exceeds the jabber timer (46ms), the transmit and loopback functions will be disabled and col signal get asserted. after tx_en goes low for more than 500 ms, the tp transmitter will reactivate and col gets de- asserted. setting jabber disable will disable the jabber function. when the sqe test is enabled, a col pulse with 5-15bt is asserted after each transmitted packet. sqe is enabled in 10base-t by default, and can be disabled via sqe test inhibit.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 6 section 1: functional description document ac104x-ds00-405-r r everse p olarity d etection and c orrection certain cable plants have crossed wiring on the twisted pairs; the reversal of txin and txip. under normal circumstances this would cause the receive circuitry to reject all data. when the auto polarity disable bit is cleared, the phy has the abili ty to detect the fact that either 8 nlps or a burst of flps are inverted and automatically reverse the receiver's polarity. the polarity state is stored in the reverse polarity bit. if the auto polarity disable bit is set, then the reverse polarity bit can be written to force the polarity reversal of the rec eiver. i nitialization and s etup h ardware c onfiguration several different states of operation can be chosen through ha rdware configuration. external pins may be pulled either high or low at reset time. the combination of high and low values determines the power on state of the device. many of these pins are multi-function pins which change their meaning when reset ends. s oftware c onfiguration several different states of operation can be chosen through software configuration. please refer to the ?smi? on page 1 as well as section 3 ?register descriptions? on page 16 . led s each of the 4 ports has 3 individual led outputs available to indicate speed, duplex/collision, and link/activity. these multi- function pins are inputs during reset and led output pins thereafter. the level of these pins during reset determines their active output states. if a multi-function pin is pulled up during reset to select a particular function, then that led output would become active low, and the led circuit must be designed accordingly, and vice versa. a uto -n egotiation by definition the 10/100 transceiver is able to run at either 10mbps or 100mbps. in addition the phy is able to run in either half-duplex or full-duplex. to determine the operational state, the phy has hardware selects and software selects while also supporting auto- negotiation and parallel detection. legitimate operating states are:  10base-t half-duplex  10base-t full-duplex  100base-tx half-duplex  100base-tx full-duplex the phy can be hardware configured to force any one of the above mentioned modes. by forcing the mode, the phy will only run in that mode, hence limiting the locations where the product will operate. the phy is able to negotiate its mode of operation using the auto-negotiation mechanism defined in the clause 28 of ieee 802.3u specification. aneg can be enabled or disabled by hardware (anega pin) or software (reg. 0.12) control. when the aneg is enabled, the phy chooses its mode of operation by advertising its abilities and comparing them with the ability received from its link partner. it can be configured to advertise 100base-tx or 10base-t operating in either full- or half- duplex.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 1: functional description page 7 register 4 contains the current capabilities, speed and duplex, of the phy, determined through hardware selects or chip defaults. the contents of reg. 4 is sent to its link partner during the aneg process using fast link pulses (flps). an flp is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a link code word. after reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. therefore, the hardware has priority over software. when aneg is enabled, the phy sends out flps during the following conditions:  power on  link loss  restart aneg command by software during this period, the phy continually sends out flps wh ile monitoring the incoming flps from the link partner to determine their optimal mode of operation. if flps are not detected during this phase of operation, parallel detection mode is entered (see below). when the phy receives 3 identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words in reg. 5, sets the acknowledge bit it the generated flps, and waits to receive 3 identical code word with the acknowledge bit set from the link partner. once this occurs the phy configures itself to the highest technology that is common to both ends. the technology priorities are: 1 100base-tx, full-duplex 2 100base-tx, half-duplex 3 10base-t, full-duplex 4 10base-t half-duplex. once the aneg is complete, reg. 1.5 is set, reg. 1.[14:11] reflects negotiated speed and duplex mode, and the phy enters the negotiated transmission and reception state. this state will not change until link is lost or the phy is reset through eith er hardware or software, or the restart negotiation bit (reg. 0.9) is set. p arallel d etection because there are many devices in the field that do not support the aneg process, but must still be communicated with, it is necessary to detect and link through the parallel detection process. the parallel detection circuit is enabled in the absence of flps. the circuit is able to detect:  normal link pulse (nlp)  10base-t receive data  100base-tx idle the mode of operation gets configured based on the technology of the incoming signal. if any of the above is detected, the device automatically configures to match the detected operating speed in the half-duplex mode. this ability allows the device to communicate with the legacy 10base-t and 100base-tx systems, while maintaining the flexibility of auto-negotiation.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 8 section 1: functional description document ac104x-ds00-405-r a utomatic mdi/mdix c onfiguration the ac104x supports the mdi/mdix automatic configuration function. the automatic mdi/mdix is intended to eliminate the need for crossover cables between similar devices. the assignment of pin-outs for the auto-mdi/mdix is shown below: d iagnostics l oopback o peration local loopback is provided for testing purposes. it can be enabled by writing to reg. 0.14. the local loopback routes transmitted data through the transmit path back to the receiving path's clock and data recovery module. the loopback data are presented to the pcs in 5 bits symbol format. this loopback is used to check the operation of the 5-bit symbol decoder and the phase locked loop circuitry. in local loopback, the sd output is forced to logic one and txop/n outputs are tri-stated. c able l ength i ndicator in 100base-t mode, the phy can detect the approximate length of the cable it's attached and display the result in reg. 20.[7:4]. a reading of [0000] translates to < 10m cable used, [0001] translates to ~ 10 meter of cable, and [1111] translates to 150 meter cable. the cable length value can be used by the network manage to determine the proper connectivity of the cable and to manage the cable plant distribution r eset and p ower the phy can be reset in three ways:  during initial power on.  hardware reset: a logic low signal of 150 s pulse width is applied to rst* pin.  software reset: write a one to smi reg. 0.15. the power consumption of the device is significantly reduced due to its built-in power management features. separate power supply lines are used to power the 10base-t circuitry and the 100base-tx circuitry. therefore, the two circuits can be turned on and turned off independently. when the phy is set to operate in 100base-tx mode, the 10base-t circuitry is powered down, and vice versa. the following power management features are supported:  power down mode: this can be achieved by writing to register 0.11 or pulling pwrdn pin high. during power down mode, the device is still be able to interface through the mdc/mdio management interface. table 1: auto-mdi/mdix pinout assignments contact phy mdi mdix 1 txop txop rxip 2 txon txon rxin 3 rxip rxip txop 4n/cn/cn/c 5n/cn/cn/c 6 rxin rxin txon 7n/cn/cn/c 8n/cn/cn/c
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 1: functional description page 9  energy detect/power saving mode: energy detect mode turns off the power to select internal circuitry when there is no live network connected. energy detect (ed) circuit is always turned on to monitor if there is a signal energy present on the media. the smi circuitry is also powered on and re ady to respond to any management transaction. the transmit circuit still send out link pulses with minimum power consumpt ion. if a valid signal is received from the media, the device powers up and resumes normal transmit/receive operation. (patent pending)  reduced transmit drive strength mode: additional power saving can be gained at the phy level by designing with 1.25:1 turns magnetic ratio and asserting the tp125 pin at reset. c lock the clock input must have a ttl clock oscillator measured at 50 mhz-100ppm.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 10 section 2: pin description document ac104x-ds00-405-r section 2: pin description p in d iagram figure 2: ac104x 100-pin cvdd3 rxd0_a rxd1_a ovdd3 tx_en(b) txd0_b txd1_b cgnd3 ognd2 crs_dv(b) rx_er(b) rxd0_b rxd1_b cvdd2 refclk mdc mdio tx_en(c) ovdd2 txd0_c txd1_c ognd1 crs_dv(c) auto_mdix_dis/rx_er(c) rxd0_c rxd1_c cvdd1 tx_en(d) cgnd2 txd0_d 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rx_er(a) 81 50 txd1_d crs_dv(a) 82 49 cgnd1 cgnd4 83 48 crs_dv(d) txd1_a 84 47 phyad_st/rx_er(d) txd0_a 85 46 rxd0_d txen(a) 86 45 rxd1_d ognd3 87 44 ovdd1 leddpx(b)/phyad[4] 88 43 force100/ledspd(c) ledact_lnk(b)/phyad[3] 89 42 ledact_lnk(c) ledspd(b)/phyad[2] 90 41 dplx/leddpx(c) leddpx(a)/col_led_en 91 40 burn-in/ledspd(d) ledact_lnk(a) 92 39 anega/ledact_lnk(d) ledspd(a) 93 38 scram_en/leddpx(d) intr 94 37 nc6 rstn 95 36 nc5 gagnd 96 35 nc4 ibref 97 34 nc3 gavdd1 98 33 nc2 gavdd2 99 32 nc1 avdd8 100 31 avdd7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rxin_txon(a) rxip_txop(a) agnd1 agnd2 txop_rxip(a) txon_rxin(a) avdd2 avdd1 txon_rxin(b) txop_rxip(b) agnd3 agnd4 rxip_txop(b) rxin_txon(b) avdd3 avdd4 rxin_txon(c) rxip_txop(c) agnd5 agnd6 txop_rxip(c) txon_rxin(c) avdd5 avdd6 txon_rxin(d) txop_rxip(d) agnd7 agnd8 rxip_txop(d) rxin_txon(d) ac104x 100-pin pqfp
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 2: pin description page 11 p in d escriptions many of the pins of these devices have multiple functions . designate the multi-function pins by bolding the pin number. designers must assure that they have identified all modes of operation prior to final design. the pin assignment shown below and in the pin description table is subject to change without notice. contact altima communications inc. before implementing any design based on the information provided in this data sheet. signal types:  i = inputs  o = outputs  z = high impedance  u = pull up  d = pull down  a = analog signal  * = active low signal  nc = no connect pin table 2: mdi (media dependent interface) pins pin name pin # type description rxin_txon(a) rxin_txon(b) rxin_txon(c) rxin_txon(d) 1 14 17 30 ai/o ai/o ai/o ai/o mdi: receiver input negative for both 10base-t and 100base-tx. mdix: transmitter output negative for both 10base-t and 100base-tx. rxip_txop(a) rxip_txop(b) rxip_txop(c) rxip_txop(d) 2 13 18 29 ai/o ai/o ai/o ai/o mdi: receiver input positive for both 10base-t and 100base-tx. mdix: transmitter output positive for both 10base-t and 100base-tx. txon_rxin(a) txon_rxin(b) txon_rxin(c) txon_rxin(d) 6 9 22 25 ai/o ai/o ai/o ai/o mdi: transmitter output negative for both 10base-t and 100base-tx. mdix: receiver input negative for both 10base-t and 100base-tx. txop_rxip(a) txop_rxip(b) txop_rxip(c) txop_rxip(d) 5 10 21 26 ai/o ai/o ai/o ai/o mdi: transmitter output positive for both 10base-t and 100base-tx. mdix: receiver input positive for both 10base-t and 100base-tx.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 12 section 2: pin description document ac104x-ds00-405-r table 3: rmii (reduced media independent interface) pins pin name pin # type description txd[1:0](a) txd[1:0](b) txd[1:0](c) txd[1:0](d) 84, 85 74, 75 60, 61 50, 51 i,d i,d i,d i,d rmii transmit data. the mac sources t he txd[1:0](n) synchronous with refclk when tx_en(n) is asserted. tx_en(a) tx_en(b) tx_en(c) tx_en(d) 86 76 63 53 i,d i,d i,d i,d rmii transmit enable. tx_en(n) is asserted high by the mac to indicate that valid data for transmission is presented on the txd[1:0](n). rxd[1:0](a) rxd[1:0](b) rxd[1:0](c) rxd[1:0](d) 78,79 68,69 55,56 45,46 o o o o rmii receive data. the phy sources the rxd[1:0](n) synchronous with refclk when crs_dv(n) is asserted. crs_dv(a) crs_dv(b) crs_dv(c) crs_dv(d) 82 71 58 48 o o o o crs_dv(n) is asserted high when media is non-idle. rx_er(a) rx_er(b) rx_er(c) rx_er(d) 81 70 57 47 o o i/o,d i/o,d rmii receive error. when rx_er is asserted high, it indicates an error has been detected during frame reception. refclk 66 i reference clock input ? 50 mhz-100ppm ttl table 4: smi ( serial management interface) pins pin name pin # type description mdio 64 i/o, d management data input/output. bi-directional data interface. 1.5k pull up resistor required (as specified in ieee-802.3). mdc 65 i, d management data clock. 0 to 25 mhz clock sourced by the mac for transfer of mdio data. intr 94 z interrupt. see register 17. the intr pin has a high impedance output. a 1k ? re- sister pull-up is required for this active low signal.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 2: pin description page 13 table 5: phy address pins pin name pin # type description phyad_st 47 i/o,d this pin sets the two least significant digits of the phy address for all four ports ac- cording to the two options below: 1 at reset = a-xxx00, b-xxx01, c-xxx10, d-xxx11 0 at reset = a-xxx01, b-xxx10, c-xxx11, d-xxx00 phyad [4] phyad [3] phyad [2] 88 89 90 i/o i/o i/o phy address [4:2]. these pins set the three most significant digits for the phy ad- dress. phyad [4] sets the most significant digit. phyad [1:0] are internally set ac- cording to the status of phyad_st. the phyad determines the scramble seed, and helps to reduce emi when there are multiple ports switching at the same time. table 6: mode pins pin name pin # type description auto_mdix_dis 57 i/o auto-mdix disable. pulled up upon reset will turn off the auto-mdix future. dplx 41 i/o full-duplex mode. the default value of the control bit (reg.0.8) is dependent on this pin when the anega pin is pulled-low/asserted-low. when asserted high, the phy operates in full-duplex mode as the default mode. force100 43 i/o force100: force 100base-tx operat ion. when this signal is pulled high and anega is low upon reset, all ports are forced to 100base-tx operation. when asserted low and anega is low, all ports are forced to 10base-t operation. when anega is high, force100 has no effect on operation. scram_en 38 i/o scrambler enable. pulled high under normal circumstances to enable scrambler and de-scrambler. if pulled low upon reset, scrambling functions will be disabled. anega 39 i/o auto-negotiation ability. asserted high means auto-negotiation enable while low means manual selection through dplx, force100. burn_in* 40 i/o burn-in mode. burn-in mode for reliability assurance control. this is reserved for factory testing only. col_led_en 91 i/o if pulled high with 10k ? , leddpx pins will toggle whenever there is a collision detected in half-duplex. (should be pulled-high!) if pulled low, leddpx pins will not toggle.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 14 section 2: pin description document ac104x-ds00-405-r polarity of leds is determined by polarity of mode pins. table 7: led pins pin name pin # type description leddpx[a] leddpx[b] leddpx[c] leddpx[d] 91 88 41 38 o o o o port[n] duplex led. active state indicates full-duplex. in half-duplex, this pin is designed to blink to indicate collision. ledact_lnk[a] ledact_lnk[b] ledact_lnk[c] ledact_lnk[d] 92 89 42 39 o o o o port[n] activity/link led. active state indicates a valid link. when there is receive or transmit activity, led toggles between high and low for 250 ms interval. ledspd[a] ledspd[b] ledspd[c] ledspd[d] 93 90 43 40 o o o o port[n] speed led. active state indicates 100base-tx mode. table 8: miscellaneous pins pin name pin # type description rstn 95 i, u reset. an active low input forces a known initialization state. the reset pulse dura- tion must be > 100 us. setting mii reg. 0.15 asserts software reset, which has the same functionality as the hardware reset. reserved 32 33 34 35 36 37 ao should be left un-connected. ibref 97 a reference bias resistor. must be tied to analog ground through an external 10k ? (1%) resistor.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 2: pin description page 15 table 9: power and ground pins pin name pin # type description ovdd 44, 62, 77 p digital +2.5v power supply for i/o. ognd 59, 72, 87 g digital ground for i/o. cvdd 54, 67, 80 p digital +2.5v power supply for core logic. cgnd 49, 52, 73, 83 g digital ground for core logic. avdd 7, 8, 15, 16, 23, 24, 31, 100 p +2.5v power supply for analog circuit. agnd 3, 4, 11, 12, 19, 20, 27, 28 g ground for analog circuit. gavdd 98,99 p +2.5v power supply for common analog circuits. gagnd 96 g ground for common analog circuits.
ac104x preliminary data sheet 12/11/01 broadcom corporation page 16 section 3: register descriptions document ac104x-ds00-405-r section 3: register descriptions the first seven registers of the mii register set are defined by the mii specification. in addition to these required registers are several altima communications inc. specific registers. there are reserved registers and/or bits that are for altima internal use only. the following standard registers are supported. regi ster numbers are in decimal format; the values are in hex format. when writing to registers it is recommended that a read/modify/write operation be performed, as unintended bits may get to unwanted states. this applies to all registers, including those with reserved bits. l egend rw read and write access sc self clearing ll latch low until cleared by reading ro read only rc cleared on read lh latch high until cleared by reading table 10: registers 0-7 register description default 0 control register 3000 1 status register 7849 2 phy identifier 1 register 0022 3 phy identifier 2 register 5542 4 auto-negotiation advertisement register 01e1 5 auto-negotiation link partner ability register 0001 6 auto-negotiation expansion register 0004 7 next page advertisement register 2001
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 17 table 11: registers 8-31 register description default 8-15 reserved xxxx 16 bt and interrupt level control register 1000 17 interrupt control/status register 0000 18,19 reserved xxxx 20 cable measurement capability register xxxx 21 receive error counter register 0000 22-31 reserved xxxx table 12: register 0: control bit name description mode default 0.15 reset 1 = phy reset. this bit is self-clearing. rw/sc 0 0.14 loopback 1 = enable loopback mode. this loopbacks the txd to rxd and ignores all the activity on the cable media. 0 = normal operation. rw 0 0.13 speed select 1 = 100 mbps 0 = 10 mbps. autoneg enabled: this bit is writable but will be ignored. rw set by forc100 pin 0.12 aneg enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process. mode selection is controlled via bit 0.8, 0.13 or through the mode pins. rw set by anega 0.11 power down 1 = power down. all blocks except for smi turns off. setting pwrdn pin to high achieves the same result. 0 = normal operation. rw 0 0.10 isolate 1 = electrically isolate the phy from mii. phy is still able to response to smi. 0 = normal operation. rw 0.9 restart aneg 1 = restart auto-negotiation process. 0 = normal operation. rw/sc 0 0.8 duplex mode 1 = full-duplex. 0 = half-duplex. autoneg enabled: this bit is writable but will be ignored. the default value is 0 if auto-negotiation is enabled via pin anega. rw set by dplx and anega pin 0.7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of tx_en signal. collision test is disabled if pcsbp pin is high. collision test is enabled regardless of the duplex mode. 0 = disable col test. rw 0 0.[6:0] reserved rw 0000000
ac104x preliminary data sheet 12/11/01 broadcom corporation page 18 section 3: register descriptions document ac104x-ds00-405-r * = based on an oui is 0010a9 (hex) table 13: register 1: status bit name description mode default 1.15 100base-t4 permanently tied to zero indicates no 100base-t4 capability. ro 0 1.14 100base-tx full- duplex 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full-duplex capable. ro set by dplx pin 1.13 100base-tx half- duplex 1 = 100base-tx half-duplex capable. 0 = not tx half-duplex capable. ro 1 1.12 10base-t full- duplex 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. ro set by dplx pin 1.11 10base-t half- duplex 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. ro 1 1.[10:7] reserved ro 0000 1.6 mf preamble suppression the phy is able to perform management transaction without mdio preamble. the management interface needs minimum of 32 bits of preamble after reset. ro 1 1.5 aneg complete 1 = auto-negotiate process completed. reg. 4, 5, 6 are valid after this bit is set. 0 = auto-negotiate process not completed. ro 0 1.4 remote fault 1 = remote fault condition detected. 0 = no remote fault. this bit remains set until it is cleared by reading register 1. ro/lh 0 1.3 aneg ability 1 = able to perform auto-negotiation function, default value determined by anega pin. 0 = unable to perform auto-negotiation function. ro 1 1.2 link status 1 = link is established. if link fails, this bit clears and remains at 0 until register is read again. 0 = link has gone down. ro/ll 0 1.1 jabber detect 1 = jabber condition detect. 0 = no jabber condition detected. ro/lh 0 1.0 extended capability 1 = extended register capable. this bit is tied permanently to one. ro 1 table 14: register 2: phy identifier 1 reg.bit name description mode default 2.[15:0] oui* composed of the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. ro 0022(h)
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 19 * = based on an oui of 0010a9 (hex) table 15: register 3: phy identifier 2 bit name description mode default 3.[15:10] oui assigned to the 19th through 24th bits of the oui. ro 010101 3.[9:4] model number 6-bit manufacturer?s model number. ro 010100 3.[3:0] revision number 4-bit manufacturer?s revision number. ro 0010 table 16: register 4: auto-negotiation advertisement bit name description mode default 4.15 next page 1 = next page enabled. 0 = next page disabled. rw 0 4.14 acknowledge this bit will be set internally after receiving 3 consecutive and consistent flp bursts. ro 0 4.[13:11] reserved 0 4.10 fdfc full-duplex flow control 1= advertise that the dte(mac) has implemented both the op- tional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0= mac does not support flow control 4.9 100base-t4 technology not supported. this bit always 0 ro 0 4.8 100base-tx full-duplex 1 = 100base-tx full-duplex capable. 0 = not 100basetx full-duplex capable. rw set by dplx pin 4.7 100base-tx 1 = 100base-tx half-duplex capable. 0 = not tx half-duplex capable. rw 1 4.6 10base-t full-duplex 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. rw set by dplx pin 4.5 10base-t 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. rw 1 4.[4:0] selector field protocol selection [00001] = ieee 802.3. ro 00001
ac104x preliminary data sheet 12/11/01 broadcom corporation page 20 section 3: register descriptions document ac104x-ds00-405-r *when this register is used as next page message, the bit definition is the same as register 7. table 17: register 5: auto-negotiation link partne r ability register/link partner next page message bit name description mode default 5.15 next page 1 = link partner desires next page transfer. 0 = link partner does not desire next page transfer. ro 0 5.14 acknowledge 1 = link partner acknowledges reception of flp words. 0 = not acknowledged by link partner. ro 0 5.[13:10] reserved 5.9 100base-t4 1 = 100base-t4 supported by link partner. 0 = 100base-t4 not supported by link partner. ro 0 5.8 100base-tx full-duplex 1 = 100base -x full-duplex supported by link partner. 0 = 100base-tx full-duplex not supported by link partner. ro 0 5.7 100base-tx 1 = 100base-tx half-duplex supported by link partner. 0 = 100base-tx half-duplex not supported by link partner. ro 0 5.6 10base-t full-duplex 1 = 10 mbps full-duplex supported by link partner. 0 = 10 mbps full-duplex not supported by link partner. ro 0 5.5 10base-t 1 = 10 mbps half-duplex supported by link partner. 0 = 10 mbps half-duplex not supported by link partner. ro 0 5.[4:0] selector field protocol selection [00001] = ieee 802.3. ro 00001 table 18: register 6: auto-negotiation expansion bit name description mode default 6.[15:5] reserved ro 0 6.4 parallel detection fault 1 = fault detected by parallel detection logic, this fault is due to more than one technology detecting concurrent link up condition. this bit can only be cleared by reading register 6, using the man- agement interface. 0 = no fault detected by parallel detection logic. ro/ lh 0 6.3 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 6.2 next page able next page is supported. ro 1 6.1 page received this bit is set when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon a read of this register. ro/ lh 0 6.0 link partner aneg-able 1 = link partner is auto-negotiation capable. 0 = link partner is not auto-negotiation capable. ro 0
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 21 table 19: register 7: auto-negotiation next page transmit bit name description mode default 7.15 np 1 = another next page desired. 0 = no other next page transfer desired. rw 0 7.14 reserved ro 0 7.13 mp 1 = message page. 0 = un-formatted page. rw 1 7.12 ack2 1 = will comply with message. 0 = can not comply with message. rw 0 7.11 tog_tx 1 = previous value of transmitted link code word equals to 0. 0 = previous value of transmitted link code word equals to 1. rw 0 17.[10:0] code message/un-formatted code field. rw 001 table 20: register 16: bt and interrupt level control bit name description mode default 16.15 reserved rw 0 16.14 reserved ro 0 16.13 reserved rw 0 16.12 reserved rw 1 16.11 sqe test inhibit 1 = disable 10base-t sqe testing. 0 = enable 10base-t sqe testing, which generates a col pulse following the completion of a packet transmission. rw 0 16.10 bt normal loop-back 1 = enable 10base-t normal loop-back. 0 = disable 10base-t normal loop-back. rw 0 16.[9:6] reserved ro 0 16.5 auto polarity disable 1 = disable auto polarity detection/correction. 0 = enable auto polarity detection/correction. rw 0 16.4 reverse polarity 1= reverse polarity when register 16.5 = 0 0= normal polarity when register 16.5 = 0 if register 16.5 is set to 1, writing a one to this bit will reverse the polarity of the transmitter. rw 0 16.[3:0] reserved ro 0
ac104x preliminary data sheet 12/11/01 broadcom corporation page 22 section 3: register descriptions document ac104x-ds00-405-r table 21: register 17: interrupt control/status bit name description mode default 17.15 jabber_ie jabber interrupt enable. rw 0 17.14 rx_er_ie receive error interrupt enable. rw 0 17.13 page_rx_ie page received interrupt enable. rw 0 17.12 pd_fault_ie parallel detection fault interrupt enable. rw 0 17.11 lp_ack_ie link partner acknowledge interrupt enable. rw 0 17.10 link_status_change_ie link status change interrupt enable. rw 0 17.9 r_fault_ie remote fault interrupt enable. rw 0 17.8 aneg_comp_ie auto-negotiation complete interrupt enable. rw 0 17.7 jabber_int this bit is set when a jabber event is detected. rc 0 17.6 rx_er_int this bit is set when rx_er transitions high. rc 0 17.5 page_rx_int this bit is set when a new page is received during aneg. rc 0 17.4 pd_fault_int this bit is set when parallel detect fault is detected. rc 0 17.3 lp_ack_int this bit is set when the flp with acknowledge bit set is received. rc 0 17.2 link_status_changed_int this bit is set when link status switches are changed. rc 0 17.1 r_fault_int this bit is set when remote fault is detected. rc 0 17.0 aneg _comp int this bit is set when aneg is complete. rc 0
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 23 table 22: register 18: diagnostic bit name description mode default 18.15 lp_inbk link pulse loopback. 1 = loopback the link pulse for auto-negotiation testing. rw 0 18.14 send_nlp 1 = force link pulse generator to send nlp even in auto- negotiation mode. rw 0 18.13 force link pass bt 1 = force 10base-t link pass. rw 0 18.12 force link pass tx 1 = force 100base-tx link pass. rw 0 18.11 dplx this bit indicates the result of the auto-negotiation for duplex arbitration. ro 0 18.10 speed this bit indicates the result of the auto-negotiation for data speed arbitration. ro 0 18.9 rx_pass in 10base-t mode, this bit indicates the manchester data has been detected. in 100base-t mode, it indicates valid signal has been received but not necessarily locked on to. rc 0 18.8 rx_lock indicates the receive pll has locked onto the received signal for the selected speed of operation (10base-t or 100base- tx). this bit is set whenever a cycle-slip occurs, and will remain set until it is read. rc 0 18.[7:4] arb_state highest highest state of auto-negotiation state machine since reset on last read operation. rc 0000 18.[3:0] arb_state lowest lowest state of auto-negotiation state machine since reset on last read operation. rc 1111
ac104x preliminary data sheet 12/11/01 broadcom corporation page 24 section 3: register descriptions document ac104x-ds00-405-r table 23: register 19: test register bit name description mode default 19.[15:9] reserved reserved. rw 00 19.8 tx_fef 1 = force fef transmit. rw 0 19.7 error counter full 1 = error count full. when set indicates the rx_error counter full in the receiver circuit. this event will cause de-scrambler to reset. rc 0 19.6 err cnt disable 1 = disable error counter in the receiver module. rw 0 19.5 disable watch dog timer for decipher 1 = disable watch dog timer. 0 = enable watch dog timer. rw 0 19.4 low power mode disable 1 = disable advanced power saving mode. 0 = enable advanced power saving mode. rw 0 19.3 enable digital loopback 1 = enable digital loop back. rw 0 19.2 test loop back 1 = enable analog test loop back. rw 0 19.1 remote loop back 1 = enable analog remote loop back. rw 0 19.0 jabber disable 1 = disable jabber. rw 0 table 24: register 20: cable measurement capability bit name description mode default 20.15 reserved rw 1 20.14 reserved rw 1 20.[13:9] reserved ro 0 20.8 adaption disable 1 = disable adaption. rw 0 20.[7:4] cable measurement capability these bits can be used as cable length indicator. the bits are incremented from 0000 to 1111, with an increment of approximately 10 meters. the equivalent is 0 to 32 db with an increment of 2 db @ 100 mhz. the value is a read back from the equalizer, and the measured value is not absolute. these bits are only applicable to the 100base-tx mode. rw x 20.[3:0] adaption low limit value adaption setting, when the sd signal is first detected. ro x
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 25 table 25: register 21: receive error counter bit name description mode default 21.[15:0] rx_er counter count receive error events. ro 0 table 26: register 22: power management bit name description mode default 22.[15:14] reserved ro 00 22.13 pd_pll 1 = power down pll circuit. ro x 22.12 pd_equal 1 = power down equalizer circuit. ro x 22.11 pd_bt_rcvr 1 = power down 10 base t receiver. ro x 22.10 pd_lp 1 = power down link pulse receiver. ro x 22.9 pd_en_det 1 = power down energy detect circuit. ro x 22.8 reserved ro 1 22.[7:6] reserved rw 11 22.5 msk_pll 0 = force power up pll circuit. rw 1 22.4 msk_equal 0 = force power up equalizer circuit. rw 1 22.3 msk_bt_rcvr 0 = force power up 10 base t receiver. rw 1 22.2 msk_lp 0 = force power up link pulse receiver. rw 1 22.1 msk_en_det 0 = force power up energy detect circuit. rw 1 22.0 reserved rw 1
ac104x preliminary data sheet 12/11/01 broadcom corporation page 26 section 3: register descriptions document ac104x-ds00-405-r table 27: register 23: operation mode bit name description mode default 23.[15:14] reserved rw 0 23.13 clk_rclk_save 1 = set rclk save mode. rclk will be shut off after 64 cycles of each packet. rw 0 23.12 reserved rw 0 23.11 scramble disable 1 = disable scrambler. rw reset by the scram_en pin. 23.10 serial_bt_enable 1 = enable serial bt mode. rw 0 23.9 pcsbp 1 = enable pcs bypass mode. rw 0 23.8 age timer en 1 = enable age timer in adaptation. 0 = disable age timer in adaptation. rw 0 23.7 auto mdix disable 1 = disable auto mdix feature. rw reset by the auto_m_dix_dis pin. 23.6 mdix mode 0 = mdi mode. 1 = enable mdix mode. when auto-mdix feature is enabled, this is a sta- tus bit, and is read only. when auto-mdix is disabled, this bit controls the mdi, mdix selection. rw 0 23.5 reserved ro 0 23.[4:0] dlock drop counter d lock drop counter ro xxxxx table 28: register 24: crc for recent received packet bit name description mode default 24.[15:0] crc16 crc16 value displayed. for system level test purpose. rc 0000h
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 27 table 29: common register 0: common operation mode (map to phy channel a, reg 28) bit name description mode default a.28.[15:5] reserved ro 000h a.28.4 rmii_enable 1 = put the chip in shared rmii mode. the mode1 pin should be pulled down and the mode0 pin should be pulled high for the default configuration. rw 1 a.28.3 interrupt level 1 = interrupt active high. 0 = interrupt active low. rw 0 a.28.2 act select act event selector. 1 = tx or rx activity. 0 = receive activity. rw 1 a.28.1 reserved ro 0 a.28.0 reserved rw 0 table 30: common register 1: test mode (map to phy channel a, reg 29) bit name description mode default a.29.15 reserved rw 0 a.29.[14:10] reserved ro 00010 a.29.[9:8] test channel channel to be tested. rw 00 a.29.[7:4] test mode 0000 = normal operation. rw 0000 a.29.3 burn in 1 = enable burn in test mode. 0 = normal operation. rw reset by the burn_in pin a.29.2 output disable 1 = disable all digital outputs. 0 = normal operation. rw 0 a.29.1 global phy addr enable 1 = write to phy addr 0 will write to all 4 phys on the chip. 0 = normal operation. rw 0 a.29.0 reduce timer 1 = reduce timer for auto-negotiation testing. rw 0
ac104x preliminary data sheet 12/11/01 broadcom corporation page 28 section 3: register descriptions document ac104x-ds00-405-r table 31: common register 2: analog settings (map to phy channel a, reg 30) bit name description mode default a.30[15:14] edge rate control transmit edge rate control. rw 00 a.30.[13:12] 10 squelch level 10bt slicer level control. rw 01 a.30.[11:10] slice level slicer level. rw 10 a.30.[9:8] pblw baseline wander bandwidth. rw 10 a.30.[7:4] cr_res rw 0110 a.30.[3:0] drv_res rw 0000 table 32: 4b/5b code-group table pcs code group[4:0] symbol name mii (txd/rxd [3:0]) description 11110 0 0000 data 0 01001 1 0001 data 1 10100 2 0010 data 2 10101 3 0011 data 3 01010 4 0100 data 4 01011 5 0101 data 5 01110 6 0110 data 6 01111 7 0111 data 7 10010 8 1000 data 8 10011 9 1001 data 9 10110 a 1010 data a 10111 b 1011 data b 11010 c 1100 data c 11011 d 1101 data d 11100 e 1110 data e 11101 f 1111 data f
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 3: register descriptions page 29 idle and control code 11111 i 0000 inter-packet idle; used as inter-stream fill code. 11000 j 0101 start of stream delimiter, part 1 of 2; always use in pair with k symbol. 10001 k 0101 start of stream delimiter, part 2 of 2; always use in pair with j symbol. 01101 t undefined end of stream delimiter, part 1 of 2; always use in pair with r symbol. 00111 r undefined end of stream delimiter, part 2 of 2; always use in pair with t symbol. invalid code 00100 h undefined transmit error; used to send halt code group 00000 v undefined invalid code 00001 v undefined invalid code 00010 v undefined invalid code 00011 v undefined invalid code 00101 v undefined invalid code 00110 v undefined invalid code 01000 v undefined invalid code 01100 v undefined invalid code 10000 v undefined invalid code 11001 v undefined invalid code table 33: smi read/write sequence smi read/write sequence pream (32 bits) start (2 bits) opcode (2 bits) phyad (5 bits) regad (5 bits) turnaround (2 bits) data (16 bits) idle read 1?1 01 10 aaaaa rrrrr z0 d?d z write 1?1 01 01 aaaaa rrrrr 10 d?d z table 32: 4b/5b code-group table (cont.) pcs code group[4:0] symbol name mii (txd/rxd [3:0]) description
ac104x preliminary data sheet 12/11/01 broadcom corporation page 30 section 3: register descriptions document ac104x-ds00-405-r figure 3: led configurations table 34: led configurations mode leddpx ledact ledspd 10m link on off 10m hdx transmit off toggle off 10m hdx receive off toggle off 10 hdx collision on during collision toggle off 10m fdx transmit on toggle off 10m fdx receive on toggle off 100m link on on 100m hdx transmit off toggle on 100m hdx receive off toggle on 100 hdx collision on during collision toggle on 100m fdx transmit on toggle on 100m fdx receive on toggle on 300 10k 300 10 k vcc multi function led pin pulled high for reset. multi function led pin pulled low for reset.
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 4: electrical characteristics page 31 section 4: electrical characteristics a bsolute m aximum r atings storage temperature...............................-40 o c to +125 o c vcc supply referenced to gnd............. -0.25v to +2.75v digital input voltage................................. -0.33v to +3.63v dc output voltage.....................................-0.25v to +2.75v o perating r ange operating temperature (ta)............................ 0 o c to +70 o c vcc supply voltage range (vcc)......................2.375v to 2.625v note the following electrical characteristics are design goal rather than characterized numbers. table 35: dc characteristics (0 o c < ta < 70 o c, 2.375v < v cc < 2.625v, unless otherwise noted) parameter sym conditions min typ max units power supply current for all 4 ports icc 10 base-t, idle 10 base-t, normal activity traffic ~50% util. 10 base-t, peak continuous 100% utilization 100 base-tx 10/100 base-tx, low-power without cable auto-negotiation power down 95 290 480 348 75 68 115 310 500 360 85 80 1 ma maximum power consumption for all 4 ports p max 1.35 w ttl input high voltage v ih 2.0 v ttl input low voltage v il 0.8 v ttl input current iin vcc = 2.625v -10 10 a ttl input capacitance ciin 10 pf output high voltage voh 2.375v < vcc < 2.625v, i oh = 8 ma vcc-0.4 v output low voltage vol 2.375v < vcc < 2.625v, i ol = 8 ma 0.4 v
ac104x preliminary data sheet 12/11/01 broadcom corporation page 32 section 4: electrical characteristics document ac104x-ds00-405-r output transition time t r , t f . 2.375v < vcc < 2.625v, 20pf loading, 0 v~70 v1.5 6 ns led output current i oh 9ma output tristate leakage current |ioz| 10 a transmitter, 100base-tx (1:1 transformer ratio) tx output current high i oh 40 ma tx output current low i ol 0 a transmitter, 10base-t (1:1 transformer ratio) tx output current high i oh 100 ma tx output current low i ol 0 a table 35: dc characteristics (0 o c < ta < 70 o c, 2.375v < v cc < 2.625v, unless otherwise noted) (cont.) parameter sym conditions min typ max units
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 4: electrical characteristics page 33 table 36: ac characteristics (0 o c < ta < 70 o c, 2.375v < v cc < 2.625v, unless otherwise noted) parameter sym conditions min typ max units transmitter, 100base-tx differential output voltage, peak-to-peak v od 50 ? from each output to vcc, best-fit over 14 bit times 1.9 2.0 2.1 v differential output voltage symmetry v os 50 ? from each output to vcc, |vp+|/|vp-| 0.98 1.02 mv differential output over- shoot v oo percent of vp+ or vp- 5 % rise/fall time t r , t f 10 - 90% of vp+ or vp- 345ns duty cycle distortion deviation from best-fit time-grid, 010101 ... sequence 250 ps timing jitter unscrambled idle 1.4 ns transmitter, 10base-t differential output voltage, peak-to-peak v od 50 ? from each output to vcc, all pattern 4.5 5 5.5 v thd v hd db below fundamental, all ones data 27 db start-of-idle pulse width 350 ns
ac104x preliminary data sheet 12/11/01 broadcom corporation page 34 section 4: electrical characteristics document ac104x-ds00-405-r table 37: digital timing characteristics (0 o c preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 4: electrical characteristics page 35 figure 4: mdc/mdio timing diagram 1 table 38: digital timing characteristics (0 o c ac104x preliminary data sheet 12/11/01 broadcom corporation page 36 section 4: electrical characteristics document ac104x-ds00-405-r figure 5: mdc/mdio timing diagram 2 table 39: mdc/mdio timing parameter sym conditions min typ max unit setup time relative to the rising edge of mdc. t9 mdc is a 2.5 mhz output clock from the mac controller. 10 - - ns hold time relative to the rising edge of mdc. t10 mdc is a 2.5 mhz output clock from the mac controller. --10ns output delay relative to the rising edge of mdc. t11 mdc is a 2.5 mhz output clock from the mac controller. 0 20 300 ns t11 mdc 2.5 m hz m d io d a t a read cycle
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 4: electrical characteristics page 37 r ecommended t ermination contact altima communications inc. for the latest component value recommendations. figure 6: termination figure ac104x-qf txon txop ibref rxip rxin 1 tx+ 2 tx- 3 rx+ 4 unused 5 unused 6 rx- 7 unused 8 unused rj45 tc td+ td- rd+ rd- tx+ tx - rx+ rx - cmgnd transformer (auto mdi/mdix) 2.5v chassis gnd 75 ? x 3 4 9. 9 ? 4 9. 9 ? 0.1 ? 49.9 ?
ac104x preliminary data sheet 12/11/01 broadcom corporation page 38 section 4: electrical characteristics document ac104x-ds00-405-r p ower and g round f iltering contact altima communications inc. for the latest component value recommendations. figure 7: power and ground ground power .1 uf cap ac104x-qf components placed < 3mm from pin 80 77 73 72 62 59 54 52 3 4 7 8 11 12 15 16 19 20 23 24 27 28 83 87 96 98 99 100 49 44 31
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 5: package drawing page 39 section 5: package drawing figure 8: package drawing table 40: package drawing n a a1 a2 b d d1 e e1 e l l1 100 3.40 max 0.25 min 2.70 + 0.2 0.3 + 0.1 23.20 + 0.25 20.00 + 0.10 17.20 + 0.25 14.00 + 0.10 0.65 0.88 + 0.2 1.60 + 0.12
ac104x preliminary data sheet 12/11/01 broadcom corporation page 40 section 6: packaging thermal characteristics document ac104x-ds00-405-r section 6: packaging thermal characteristics 100pqfp p ackage theta jc ( c/w) at max junction temperature of 125 c. table 41: 100pqfp package thermal characteristics airflow (feet per minute) 0 100 200 400 600 theta ja ( c/w) t9 10 - - ns
preliminary data sheet ac104x 12/11/01 broadcom corporation document ac104x-ds00-405-r section 7: ordering information page 41 section 7: ordering information part number package ambient temperature ac104xkqm 100-pin pqfp 0c to 70c
document ac104x-ds00-405-r ac104x preliminary data sheet 12/11/01 altima communications, inc. a wholly owned subsidiary of broadcom corporation p.o. box 57013 16215 alton parkway irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom corporation reserves the right to make changes without further notice to any products or data herein to improve reliab ility, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.


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